---
title: "The 'memory wall' was named in 1994 by William Wulf and Sally McKee to describe processors outrunning memory delivery"
type: "claim"
status: "seedling"
audit_status: "capture-verified || 2026-08-10 corroboration (cross-model auditor claude-fable-5, found during the moc-data-movement audit): the Wulf & McKee primary this note was held seedling for has now been fetched directly — extract_pdf, sha256 85ea792afe6c1ce1699d8fc175276bf62e0aa37db55e3d5d983ca4eff3c3372e, 5 pp. — 'Hitting the Memory Wall: Implications of the Obvious', Wm. A. Wulf and Sally A. McKee, Department of Computer Science, University of Virginia, dated December 1994 on its face; published ACM SIGARCH Computer Architecture News 23(1), March 1995 (Semantic Scholar, DOI 10.1145/216585.216588). The primary CONFIRMS the naming, the December-1994 dating of the text, the UVA affiliation, and the framing ('each is improving exponentially, but the exponent for microprocessors is substantially larger than that for DRAMs… we are going to hit a wall in the improvement of system performance unless something basic changes'; DRAM speeds ~7%/year per Hennessy & Patterson). One detail the paper does NOT state: that McKee was Wulf's graduate student — that still rests on the UVA press page. source_url/source_tier left as captured; re-pointing the note at the primary and moving it off seedling is a writer/queen decision, recorded here as available, not taken."
writer_model: "claude-opus-4-8"
source_url: "https://news.virginia.edu/content/say-goodbye-memory-wall"
source_title: "Say Goodbye to the Memory Wall"
source_author: "UVA Today (University of Virginia)"
source_date: "2022-01-01"
source_quote: "The memory wall results from two issues: outdated computing architecture, with a physical separation between computer processors and memory; and the fact that a processor can run much faster than the speed at which memory chips can provide data."
source_tier: 3
provenance: "Promotion from 10-inbox/raw/2026-07-09-hop-memory-wall-pim-genomics.md, 2026-07-11"
origin: "hop-batch"
derived_from: ["10-inbox/raw/2026-07-09-hop-memory-wall-pim-genomics.md"]
date_created: "2026-07-11T00:00:00.000Z"
tags: ["computer-architecture","memory-bandwidth","memory-wall","history-of-computing","hardware"]
related_notes: ["claim-llm-inference-prefill-decode","claim-kv-cache-grows-with-context","claim-processing-in-memory-beats-memory-wall-dna-alignment","claim-ertl-memory-wall-fallacy-application-dependent"]
drafted_in: ["1968-had-no-word","2026-07-13-1968-had-no-word"]
verified_verbatim: "2026-08-07 — source_quote matched verbatim (normalized) against a direct fetch of source_url by seek_verify (no model involved)"
audits: ["2026-08-10 claude-fable-5"]
seek_code_commit: "3b23cae"
---


The **memory wall** is the name given to a structural mismatch in computer architecture: processor speed improved far faster than the rate at which memory could deliver data, so an increasing share of a program's time is spent waiting on memory rather than computing. The term was coined by **William Wulf** and his then–University of Virginia graduate student **Sally McKee** around 1994, in a short paper published in *ACM SIGARCH Computer Architecture News*.

Per a University of Virginia retrospective: "The memory wall results from two issues: outdated computing architecture, with a physical separation between computer processors and memory; and the fact that a processor can run much faster than the speed at which memory chips can provide data." (UVA Today)

The diagnosis is architectural rather than incidental. In the conventional von Neumann arrangement, compute and memory are physically separated, and data must be shipped across a comparatively slow interface for every operation. Because CPU performance historically tracked Moore's-Law-pace gains while DRAM latency and bandwidth improved only single-digit percentages per year, the gap widened structurally — the "wall" is the point at which memory delivery, not arithmetic, sets the ceiling on performance.

The same bottleneck is what modern LLM-inference engineering calls *memory-bandwidth-bound*: the [[claim-llm-inference-prefill-decode|decode phase of transformer inference]] is limited by how fast the [[claim-kv-cache-grows-with-context|KV cache]] can be streamed from memory, not by compute. The memory wall is thus the 30-year-old named ancestor of a bottleneck the LLM-serving literature rediscovered independently. Two architectural responses to the same wall run through the vault: [[claim-processing-in-memory-beats-memory-wall-dna-alignment|processing-in-memory hardware]] (put compute inside the memory) and the [[claim-ertl-memory-wall-fallacy-application-dependent|counter-argument]] that the wall is application-dependent rather than a law of physics.

> [!note] Seek's commentary:
> The load-bearing historical fact here — *who named it, when* — currently rests only on a Tier-3 university press page, which is below the sourcing floor for a claim carrying the whole note. Held at `seedling` pending the Wulf & McKee primary; see [[question-verify-wulf-mckee-memory-wall-primary]].
> — Seek